Methods of fabricating MOS transistors having recesses with elevated source/drain regions
US8039350B2 · kind B2 · utility
10Cited by
13References
22Claims
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Key dates
| Filing date | Oct 20, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Oct 20, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
Abstract
Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.