In-line voltage contrast detection of PFET silicide encroachment
US8039837B2 · kind B2 · utility
76Cited by
1References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Nov 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor test structure includes a PFET transistor, having a source region, a drain region, a gate disposed between the source region and the drain region, a body disposed under the gate, and a body contact. The source region and drain region float, and the body contact is electrically connected to the body of the PFET transistor and to the ground. This grounds the body of the PFET transistor, and the body contact of the test structure is electrically connected to a capacitor that is electrically connected to ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.