(110)-oriented p-channel trench MOSFET having high-K gate dielectric
US8039877B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jun 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a field effect transistor having a heavily doped p-type (110) semiconductor layer over a metal substrate starts with providing a heavily doped p-type (110) silicon layer, and forming a lightly doped p-type (110) silicon layer on the P heavily doped-type (110) silicon layer. The method also includes forming a p-channel MOSFET which has a channel region along a (110) crystalline plane in the lightly doped p-type (110) silicon layer to allow a current conduction in a <110> direction. The p-channel MOSFET also includes a gate dielectric layer having a high dielectric constant material lining the (110) crystalline plane. The method further includes forming a top conductor layer overlying the lightly doped p-type (110) silicon layer and a bottom conductor layer underlying the heavily doped p-type (110) silicon layer. A current conduction from the top conductor layer to the bottom conductor layer is characterized by a hole mobility along a <110> crystalline orientation and on a (110) crystalline plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.