Split charge storage node outer spacer process
US8039891B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2010 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Dec 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory cells containing two split sub-lithographic charge storage nodes on a semiconductor substrate and methods for making the memory cells are provided. The methods can involve forming two split sub-lithographic charge storage nodes by using spacer formation techniques. By removing an exposed portion of a fist poly layer between sloping side surfaces or outer surfaces of spacers while leaving portions of the first poly layer protected by the spacers, the method can provide two split sub-lithographic first poly gates. Further, by removing an exposed portion of a charge storage layer between sloping side surfaces or outer surfaces of spacers, the method can provide two split, narrow portions of the charge storage layer, which subsequently form two split sub-lithographic charge storage nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.