CMOS inverter coupling circuit comprising vertical transistors
US8039893B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 19, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Sep 19, 2028 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
There is provided a semiconductor device formed of a highly integrated high-speed CMOS inverter coupling circuit using SGTs provided on at least two stages. A semiconductor device according to the present invention is formed of a CMOS inverter coupling circuit in which n (n is two or above) CMOS inverters are coupled with each other, each of the n inverters has: a pMOS SGT; an nMOS SGT, an input terminal arranged so as to connect a gate of the pMOS SGT with a gate of the nMOS SGT; an output terminal arranged to connect a drain diffusion layer of the pMOS SGT with a drain diffusion layer of the nMOS SGT in an island-shaped semiconductor lower layer; a pMOS SGT power supply wiring line arranged on a source diffusion layer of the pMOS SGT; and an nMOS SGT power supply wiring line arranged on a source diffusion layer of the NMOS SGT, and an n−1th output terminal is connected with an nth input terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.