Methods for forming planarized hermetic barrier layers and structures formed thereby
US8039920B1 · kind B1 · utility
4Cited by
8References
8Claims
0Family size
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Key dates
| Filing date | Nov 17, 2010 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Nov 17, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and associated structures of forming a microelectronic structure are described. Those methods may comprise forming a conductive material in an interconnect opening within an interlayer dielectric material that is disposed on a substrate, forming a low density dielectric material on a surface of the dielectric layer and on a surface of the conductive material, and forming a high density dielectric barrier layer on the low density dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.