Method and apparatus for configuring the internal memory cells of an integrated circuit
US8040153B1 · kind B1 · utility
2Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2010 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jan 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method and apparatus for configuring the internal memory cells of an integrated circuit through the logic fabric are disclosed. For example, an integrated circuit according to one embodiment includes a logic fabric and a plurality of input/output blocks coupled to the logic fabric, wherein the plurality of input/output blocks is positioned around the periphery of the logic fabric. The plurality of input/output blocks therefore forms a ring around the logic fabric, wherein a data path and a clock path are formed along the periphery of the logic fabric through the plurality of input/output blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.