System and method for load balancing a video signal in a multi-core processor
US8041132B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 27, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Aug 18, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/61
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Sequential video data frames are encoded using cores including a first core and a second core. A first beginning frame is divided into slices. The first core is assigned to process a first slice. The second core is assigned to process a second slice. The first beginning frame is processed using the cores which results in a first ending frame in which the first slice was partitioned into a third slice and a fourth slice. The third slice was processed by the first core. The fourth slice and the second slice were processed by the second core. A second beginning frame, which immediately follows the first ending frame, is divided into a second plurality of slices. The first core is assigned to the third slice. The second core is assigned to a fifth slice which has a size equal to a sum of the second and fourth slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.