Patent · US Active

Bus termination system and method

US8041865B2 · kind B2 · utility

10Cited by

15References

66Claims

0Family size

Assignee

Qimonda AG · DE

Inventors

Michael Bruennert · Munich, DE
Peter Gregorius · Munich, DE
Georg Braun · Hersbruck, DE
Andreas Gaertner · Munich, DE
Hermann Ruckerbauer · Radolfzell, DE
George Alexander · Durham, US
Johannes Stecker · Birkenfeld, DE

Key dates

Filing date	Aug 4, 2008
Grant date	Oct 18, 2011
Priority date	—
Expiry date	Dec 23, 2028

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4086
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory system includes a number of integrated circuit chips coupled to a bus. Each of the integrated circuit chips has an input/output node coupled to the bus, the input/output node having a programmable on-die termination resistor. The input/output node of one of the integrated circuit chips is accessed via the bus. The programmable on-die termination resistor of each of the integrated circuit chips is independently set to a termination resistance. The termination resistance is determined by a transaction type and which of the plurality memory devices is being accessed, which information can be transmitted over a separate transmission control bus.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.