System and method for fetching information to a cache module using a write back allocate algorithm
US8041899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2008 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Mar 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0879
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write back allocate system that includes: (i) a store request circuit; (ii) a processor, adapted to generate a store request that comprises an information unit and an information unit address; and (iii) a cache module, connected to the store request circuit and to a high level memory unit. A single cache module line includes multiple segments, each segment is adapted to store a single information unit. A content of a cache module line is retrieved from the high level memory unit by generating a fetch burst that includes multiple segment fetch operations. The store request circuit includes a snooper and a controller. The snooper detects a portion of an address of a cache segment of a cache line that is being fetched during a fetch burst. The controller is adapted to request from the cache module to receive the information unit before a completion of the fetch burst if the portion of the address of the cache segment matches a corresponding portion of the information unit address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.