Processor and method for controlling memory
US8041903B2 · kind B2 · utility
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17References
17Claims
0Family size
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Key dates
| Filing date | Feb 17, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jan 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/253
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor and a memory controlling method. The processor enables a Scratch-Pad Memory (SPM) to prepare data that a processor core intends to process, using a data management unit including a data cache, thereby increasing a data processing rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.