Inventor · Seoul, KR

Kwon Taek Kwon

22Patents
2h-index
24Co-inventors
53Inventor score

Filing activity: Oct 22, 2007 → Jun 20, 2017

Most-cited inventions

PatentTitleAreaCited byStatus
US9043805B2 Reconfigurable processor and method Physics 4 Active
US9449421B2 Method and apparatus for rendering image data Physics 3 Active
US9323717B2 Processor and system for processing stream data at high speed Physics 2 Active
US9741155B2 Apparatus and method for tile-based graphic data rendering Physics 2 Active
US9405546B2 Apparatus and method for non-blocking execution of static scheduled processor Physics 2 Active
US9830264B2 Cache memory system and operating method for the same Emerging Cross-Sectional Technologies 2 Active
US8214617B2 Apparatus and method of avoiding bank conflict in single-port multi-bank memory system Physics 2 Active
US10331448B2 Graphics processing apparatus and method of processing texture in graphics pipeline Physics 2 Active
US8458389B2 Apparatus and method for converting protocol interface Physics 1 Active
US9639971B2 Image processing apparatus and method for processing transparency information of drawing commands Physics 1 Active
US9519488B2 External intrinsic interface Physics 1 Active
US8144162B2 Method and apparatus for rendering three dimensional graphics data Physics 1 Active
US8862825B2 Processor supporting coarse-grained array and VLIW modes Physics 1 Active
US9013495B2 Method and apparatus for rendering Physics 0 Active
US9830721B2 Rendering method and apparatus Physics 0 Active
US9218308B2 Apparatus and method for arbitrating bus Physics 0 Active
US10229524B2 Apparatus, method and non-transitory computer-readable medium for image processing based on transparency information of a previous frame Physics 0 Active
US8041903B2 Processor and method for controlling memory Physics 0 Active
US8605101B2 Apparatus and method of reading texture data for texture mapping Physics 0 Active
US9727474B2 Texture cache memory system of non-blocking for texture mapping pipeline and operation method of texture cache memory Physics 0 Active
US8587592B2 Tile-based rendering apparatus and method Physics 0 Active
US10102005B2 External intrinsic interface Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.