Techniques for hardware-assisted multi-threaded processing
US8041929B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 2006 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Apr 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2c registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2T threads. A particular register is accessed in a register bank that has 2(C+T) registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.