Synchronization for a modeling system
US8042079B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2009 |
| Grant date | Oct 18, 2011 |
| Priority date | — |
| Expiry date | Jan 18, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.