Manufacturing method and manufacturing system of semiconductor device
US8043772B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F7/70625
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
In an exposure process forming a predetermined circuit pattern of a semiconductor device on a wafer, a resist dimension of the resist pattern formed on a wafer and a focus position in the exposure process at a past time are measured. A resist dimension and a focus position of a wafer to which the exposure process is secondly performed are estimated by using measurement results of the measured resist dimension and focus position, and a focus offset value is calculated by using estimated values of the estimated resist dimension and focus position. Then, an exposure dose is calculated with considering this focus offset value, and a resist pattern is formed on the wafer to which the exposure process is performed by using the calculated exposure dose and focus offset value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.