Semiconductor memory apparatus for controlling pads and multi-chip package having the same
US8044395B2 · kind B2 · utility
3Cited by
4References
9Claims
0Family size
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Key dates
| Filing date | Dec 30, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Sep 18, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory apparatus includes a first pad group located along a first edge of a plurality of banks, a second pad group located along a second edge of the plurality of banks opposite the first pad group, and a pad control section configured to provide first and second bonding signals and to implement control operation in response to a test mode signal and a bonding option signal to selectively employ signals from the first and second pad groups.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.