Transistors, semiconductor devices, assemblies and constructions
US8044479B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 2009 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Dec 19, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments disclosed herein include methods in which a pair of openings are formed into semiconductor material, with the openings being spaced from one another by a segment of the semiconductor material. Liners are formed along sidewalls of the openings, and then semiconductor material is isotropically etched from bottoms of the openings to merge the openings and thereby completely undercut the segment of semiconductor material. Embodiments disclosed herein may be utilized in forming SOI constructions, and in forming field effect transistors having transistor gates entirely surrounding channel regions. Embodiments disclosed herein also include semiconductor constructions having transistor gates surrounding channel regions, as well as constructions in which insulative material entirely separates an upper semiconductor material from a lower semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.