Patent · US Active

Low jitter large frequency tuning LC PLL for multi-speed clocking applications

US8044724B2 · kind B2 · utility

42Cited by

6References

10Claims

0Family size

Assignee

MOSYS, INC. · US

Inventors

Chethan Rao · San Jose, US
Alvin Wang · Fremont, US
Shaishav Desai · Sunnyvale, US

Key dates

Filing date	Apr 27, 2009
Grant date	Oct 25, 2011
Priority date	—
Expiry date	May 12, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L7/183
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The subject innovation relates to systems and/or methodologies for generating a low jitter large frequency tuning LC-based phase-locked loop circuit for multi-speed clocking applications. In addition to a plurality of noise reduction features, the phase-locked loop includes programmable charge pump and loop filter that enable a wide loop bandwidth, a programmable VCO that enables a wide VCO frequency range and a per lane clock divider that further enables a wide PLL frequency range. Furthermore, an auto-calibration circuit ensures that the VCO included in the PLL receives the optimum current for noise reduction across the VCO frequency range.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.