Low power, high speed receiver circuit for use in a semiconductor integrated circuit
US8045647B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Apr 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.