High performance CMOS radio frequency receiver
US8045943B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 2008 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Jun 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance radio frequency receiver includes a low noise amplifier with large binary and stepped gain control range, controlled impedance, and enhanced blocker immunity, for amplifying and converting a radio frequency signal to a current; a pulse generator for generating in-phase and quadrature pulses; a crossover correction circuit and pulse shaper for controlling a crossover threshold of the pulses and interaction between in-phase and quadrature mixers; and a double balanced mixer for combining the RF signal with the pulses to generate an intermediate frequency or baseband zero intermediate frequency current-mode signal. The in-phase and quadrature pulses have a duty cycle of 20-35%. The intermediate frequency signal and second order harmonics may be filtered with a high frequency low pass filter and a current injected complex direct-coupled filter. Decreased die size, current drain, cost, and complexity, as well as improvements in gain, 1/f noise, noise figure, sensitivity, and linearity may result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.