Area efficient memory architecture with decoder self test and debug capability
US8046655B2 · kind B2 · utility
4Cited by
22References
19Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 18, 2006 |
| Grant date | Oct 25, 2011 |
| Priority date | — |
| Expiry date | Nov 2, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1206
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated test device reduces external wiring congestion to a memory. The integrated test device provides for separate decoder testing and debugging to find specific errors in the memory. The device also helps in reducing the complexity of the test of external BIST. Furthermore, the number of clock cycles required for the decoder testing for an N-address memory is reduced from 4N cycles to N clock cycles. Additionally, the access time for the memory is reduced as the test device is used as a pipelining device in normal operation mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.