SOI semiconductor device with reduced topography above a substrate window area

US8048726B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Jens Heinrich · Radeberg, DE
• Kai Frohberg · Meißen, DE
• Sven Mueller · Rockenberg, DE
• Kerstin Ruttloff · Frankenberg/Sachsen, DE

Key dates

• Filing date: Oct 28, 2010
• Grant date: Nov 1, 2011
• Expiry date: Oct 28, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00

Abstract

In sophisticated SOI devices, circuit elements, such as substrate diodes, may be formed in the crystalline substrate material on the basis of a substrate window, wherein the pronounced surface topography may be compensated for or at least reduced by performing additional planarization processes, such as the deposition of a planarization material, and a subsequent etch process when forming the contact level of the semiconductor device.