Dual etch method of defining active area in semiconductor device
US8048764B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jan 6, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3081
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a hardmask for defining shallow trench isolation regions in a semiconductor substrate layer includes the steps of: depositing a hardmask layer over the semiconductor substrate layer; depositing and patterning a first photoresist layer over the hardmask layer; etching the hardmask layer after patterning the first photoresist layer to form an interim hardmask layer having at least one line feature; depositing and patterning a second photoresist layer over the interim hardmask layer; and forming a hardmask, the forming step including etching the interim hardmask layer after patterning the second photoresist layer to define a line end of the at least one line feature.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.