Package substrate with a cavity, semiconductor package and fabrication method thereof
US8049114B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | May 25, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/308
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a package substrate includes providing a cladding sheet comprising a first metal layer, a second metal layer and an intermediate layer between the first and second metal layers; etching away a portion of the first metal layer to expose a portion of the intermediate layer thereby forming a metal island body; laminating a first copper clad on the cladding sheet comprising a first copper foil and a first insulating layer; patterning the first copper foil to form a first circuit trace; patterning the second metal layer to form a second circuit trace; removing the metal island body to form a cavity in the first insulating layer; and removing the intermediate layer from bottom of the cavity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.