Semiconductor device with large blocking voltage
US8049223B2 · kind B2 · utility
4Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Feb 12, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A junction FET having a large gate noise margin is provided. The junction FET comprises an n− layer forming a drift region of the junction FET formed over a main surface of an n+ substrate made of silicon carbide, a p+ layer forming a gate region formed in contact with the n− layer forming the drift region and a gate electrode provided in an upper layer of the n+ substrate. The junction FET further incorporates pn diodes formed over the main surface of the n+ substrate and electrically connecting the p+ layer forming the gate region and the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.