Enhanced speed sorting of microprocessors at wafer test
US8049526B2 · kind B2 · utility
1Cited by
2References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2008 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | May 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus are provided for implementing optimized speed sorting of microprocessors at wafer test. A combination of speed-predicting metrics are measured early in the manufacturing process and are applied to a unique algorithm to properly sort parts into appropriate speed bins. The method significantly improves the accuracy of predicting the chip speed over conventional speed-predicting methods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.