Delay locked loop, electronic device including the same, and method of operating the same
US8049543B2 · kind B2 · utility
6Cited by
3References
17Claims
0Family size
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Key dates
| Filing date | Dec 2, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Jul 7, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00058
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay locked loop controls a plurality of delay blocks included in a delay line and thus generate a plurality of clock signals which have a frequency obtained by multiplying a frequency of a reference clock signal, an accurate phase delay, and a constant duty cycle. The delay locked loop calculates an initial delay value and applies it to the delay blocks, thereby preventing harmonic locking and reducing locking time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.