Delay-locked loop circuit controlled by column strobe write latency
US8049545B2 · kind B2 · utility
6Cited by
2References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2009 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Dec 22, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00208
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The DLL circuit includes a control circuit which controls bias currents of the unit delay circuits according to an externally input column address strobe writing latency (CWL) signal, and/or a DCC control circuit which adjusts steps of a DCC current of the DCC according to the externally input column address strobe writing latency (CWL) signal. The CWL signal may be input by a semiconductor memory device and may be indicative of a column address strobe writing latency of the semiconductor memory device. The semiconductor memory device may be a double data rate (DDR) synchronous DRAM (SDRAM) device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.