System and method for vector computations in arithmetic logic units (ALUs)
US8049760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2006 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Apr 3, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.