Integrated circuit testing using segmented scan chains
US8051348B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 2, 2010 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Nov 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31855
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.