Test method and system for characterizing and/or refining an IC design cycle
US8051398B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2007 |
| Grant date | Nov 1, 2011 |
| Priority date | — |
| Expiry date | Apr 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for refining a design cycle for an integrated circuit. An integrated circuit design is generated. A plurality of non-critical paths within the integrated circuit design are identified. A set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of non-critical paths to at least one parameter is enhanced. Each parameter is either a design parameter or a process parameter. An integrated circuit is fabricated according to the modified design. The fabricated integrated circuit is evaluated to measure a set of timing data representing each of the plurality of non-critical paths. The value of the parameter is determined from the measured set of timing data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.