Method for defect reduction for memory cell capacitors

US8053310B2 · kind B2 · utility

Assignee

• Semiconductor Manufacturing International (Shanghai) Corporation · CN

Inventors

• Ling Jin · Canton, US
• Dah Cheng Lin · Shanghai, CN
• Chin Hsing Yu · Shanghai, CN
• Meng Jan Cherng · Shanghai, CN
• Huan Sung Fu · Shanghai, CN

Key dates

• Filing date: Oct 27, 2008
• Grant date: Nov 8, 2011
• Expiry date: May 9, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D1/716

Abstract

A method for forming a cylindrical stack capacitor structure. A semiconductor substrate is provided. Storage node structures are formed in a memory cell region. A dielectric layer is formed overlying the storage node structures. A patterning and a first etching process expose the storage nodes. A polysilicon layer and a rugged polysilicon layer are formed overlying the exposed storage nodes. The memory cell region is masked, exposing a peripheral region. A chemical dry etch process removes the rugged polysilicon and the polysilicon layers in the peripheral region. The rugged polysilicon and the polysilicon layers are planarized followed by a dielectric recess. The resulting cylindrical stack capacitor structures are substantially free of defects from rugged polysilicon remaining in the peripheral region thereby improving device yield and process window.