Method for reducing chip warpage
US8053336B2 · kind B2 · utility
3Cited by
4References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Jan 5, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated circuit structure including providing a wafer comprising a front surface and a back surface, wherein the wafer comprises a chip; forming an opening extending from the back surface into the chip; filling an organic material in the opening, wherein substantially no portion of the organic material is outside of the opening and on the back surface of the wafer; and baking the organic material to cause a contraction of the organic material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.