Method for fabricating field effect transistor using a compound semiconductor
US8053345B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2010 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | May 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/015
Abstract
Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.