Method of manufacturing semiconductor device
US8053347B2 · kind B2 · utility
23Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2009 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Nov 6, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device, including forming a plurality of gate structures on a substrate, the gate structures each including a hard mask pattern stacked on a gate conductive pattern, forming an insulating layer pattern between the gate structures at least partially exposing a top surface of the hard mask pattern, forming a trench that exposes at least a top surface of the gate conductive pattern by selectively removing the hard mask pattern, and forming a silicide layer on the exposed gate conductive pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.