Input buffer and method of operation
US8054109B2 · kind B2 · utility
0Cited by
30References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2011 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Apr 8, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018528
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.