Multicore processor having storage for core-specific operational data
US8055822B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2007 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | Dec 31, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a plurality of processor cores and a readable non-volatile memory that stores information expressive of at least one operating characteristic for each of the plurality of processor cores. Also disclosed is a method to operate a data processing system, where the method includes providing a multicore processor that contains a plurality of processor cores and a readable non-volatile memory that stores information, determined during a testing operation, that is indicative of at least a maximum operating frequency for each of the plurality of processor cores. The method further includes operating a scheduler coupled to an operating system and to the multicore processor, where the scheduler is operated to be responsive at least in part to information read from the memory to schedule the execution of threads to individual ones of the processor cores for a more optimal usage of energy.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.