Patent · US Active

Data processor with hardware accelerator, accelerator interface and shared memory management unit

US8055872B2 · kind B2 · utility

10Cited by

1References

29Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Stuart David Biles · Cambridge, GB
Nigel C. Paver · Austin, US
Chander Sudanthi · Austin, US

Key dates

Filing date	Feb 21, 2008
Grant date	Nov 8, 2011
Priority date	—
Expiry date	May 16, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG06F2213/0038
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A data processing system in the form of an integrated circuit includes a general purpose programmable processor and a hardware accelerator. A shared memory management unit provides memory management operations on behalf of both of the processor core and the hardware accelerator. The processor and the hardware accelerator share a memory system. A first communication channel between the processor and the hardware accelerator communicates at least control signals therebetween. A second communication channel coupling the hardware accelerator and the memory system allows the hardware accelerator to perform its own data access operations upon the memory system.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.