Built-in self-repairable memory
US8055956B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2006 |
| Grant date | Nov 8, 2011 |
| Priority date | — |
| Expiry date | May 27, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a built-in self-repairable memory. The invention repairs a faulty IC through hard fuses, as well as through available redundancy in memories on chip. As the faults are not present in all the memories, the invention uses a lesser number of fuses to actually make a repair and thus results in a yield enhancement. The fuse data is stored in a compressed form and then decompressed as a restore happens at the power on. The fuse data interface with the memory to be repaired is serial. The serial links decreases the routing congestion and hence gain in area as well as gain in yield (due to lesser defects and reduced area).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.