Method for validating logical function and timing behavior of a digital circuit decision

US8056037B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Juergen Koehl · Holzgerlingen, DE
• Walter Pietschmann · Dornstetten, DE
• Juergen Saalmueller · Holzgerlingen, DE
• Norbert Schumacher · Bad Liebenzell, DE
• Volker Urban · Gummersbach, DE
• Joerg Walter · Lörrach, DE

Key dates

• Filing date: Sep 18, 2008
• Grant date: Nov 8, 2011
• Expiry date: Feb 21, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2119/12
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present invention relates to a method for validating the correct logical function and timing behavior of a digital circuit design within a cycle-based verification environment. The method comprises the steps of providing a VHDL description of the digital circuit design, performing a logic synthesis, wherein the VHDL description is turned into a design implementation in terms of logic gates, and creating a netlist including the elements of the digital circuit design and the connections between said elements. The method comprises the further steps of providing a transformation script with at least one transparent storage element, wherein said transparent storage element represents a path delay within the digital circuit design, creating a new netlist with the at least one transparent storage elements, running a verification, and checking if the new netlist is clean from a logical and timing point of view.