Method for fabricating semiconductor device, method for fabricating bipolar-CMOS-DMOS
US8058121B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2009 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jun 29, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/401
Abstract
A semiconductor device fabricating method is described. The semiconductor device fabricating method comprises forming an epitaxial layer on a substrate, wherein the epitaxial layer is the same conductive type as the substrate. A first doped region having the different conductive type from the epitaxial layer is formed in the epitaxial layer. An annealing process is performed to diffuse dopants in the first doped region. A second doped region and an adjacent third doped region are formed in the first doped region. The second doped region is a different conductive type from that of the first doped region, and the third doped region is the same conductive type as that of the first doped region. A gate structure is formed on the epitaxial layer covering a portion of the second and the third doped regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.