Recessed STI for wide transistors
US8058161B2 · kind B2 · utility
13Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2006 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Mar 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0158
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device having shallow trench isolation includes steps of forming a hard mask layer on the substrate surface, etching a trench through the hard mask, filling the trench with an isolation material, forming a recessed trench, and forming a serpentine gate structure to connect electronic sources and drains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.