Spin transistor using double carrier supply layer structure

US8058676B2 · kind B2 · utility

Assignee

• KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY · KR

Inventors

• Hyung Jun Kim · Seoul, KR
• Hyun Cheol Koo · Seoul, KR
• Joon Yeon Chang · Seoul, KR
• Suk Hee Han · Seoul, KR
• Kyung Ho Kim · Seoul, KR

Key dates

• Filing date: Dec 23, 2008
• Grant date: Nov 15, 2011
• Expiry date: Nov 22, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/4738

Abstract

A spin transistor includes a semiconductor substrate including a channel layer having a 2-dimensional electron gas structure and upper and lower cladding layers disposed respectively in upper and lower sides of the channel layer; ferromagnetic source and drain electrodes formed on the semiconductor substrate and disposed spaced apart from each other; a gate electrode disposed between the source electrode and the drain electrode and having a gate voltage applied thereto in order to control the spin of electrons passed through the channel layer; a first carrier supply layer disposed between the lower cladding layer and the channel layer to supply carriers to the channel layer; and a second carrier supply layer disposed between the upper cladding layer and the channel layer to supply carriers to the channel layer.