Patent · US Active

Compensation of phase lock loop (PLL) phase distribution caused by power amplifier ramping

US8058917B2 · kind B2 · utility

4Cited by

3References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Thomas Mayer · Kolbermoor, DE
Rainer Kreienkamp · Düsseldorf, DE
Jens Kissing · Kürten, DE

Key dates

Filing date	Jun 12, 2009
Grant date	Nov 15, 2011
Priority date	—
Expiry date	Jul 19, 2029

Classification

Technology area (CPC H)Electricity
CPC primaryH03L2207/50
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed herein are techniques, systems, and methods relating to compensation of phase disturbances of a phase lock-loop during power ramp up or down of a power amplifier. More specifically, a phase lock-loop is described that is able to switch between type I and type II PLL modes depending on the power state of the power amplifier without introducing additional disturbances.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.