Ferroelectric memory
US8059445B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2009 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Jan 8, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.