System, method and frame buffer logic for evicting dirty data from a cache using counters and data types
US8060700B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2008 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Feb 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/302
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for cleaning dirty data in an intermediate cache are disclosed. A dirty data notification, including a memory address and a data class, is transmitted by a level 2 (L2) cache to frame buffer logic when dirty data is stored in the L2 cache. The data classes include evict first, evict normal and evict last. In one embodiment, data belonging to the evict first data class is raster operations data with little reuse potential. The frame buffer logic uses a notification sorter to organize dirty data notifications, where an entry in the notification sorter stores the DRAM bank page number, a first count of cache lines that have resident dirty data and a second count of cache lines that have resident evict_first dirty data associated with that DRAM bank. The frame buffer logic transmits dirty data associated with an entry when the first count reaches a threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.