Apparatus and methods for low-complexity instruction prefetch system
US8060701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2006 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Nov 3, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When misses occur in an instruction cache, prefetching techniques are used that minimize miss rates, memory access bandwidth, and power use. One of the prefetching techniques operates when a miss occurs. A notification that a fetch address missed in an instruction cache is received. The fetch address that caused the miss is analyzed to determine an attribute of the fetch address and based on the attribute a line of instructions is prefetched. The attribute may indicate that the fetch address is a target address of a non-sequential operation. Another attribute may indicate that the fetch address is a target address of a non-sequential operation and the target address is more than X % into a cache line. A further attribute may indicate that the fetch address is an even address in the instruction cache. Such attributes may be combined to determine whether to prefetch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.