Method and system for clock skew reduction in clock trees
US8060770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2005 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Nov 8, 2027 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system that includes a clock tree and multiple variable delay components. The system is characterized by including a first set of fuses indicative of identities of variable delay components that belong to a first set of variable delay components, a second set of fuses indicative of delay values of the variable delay components that belong to the first set of variable delay components, and a second set of variable delay components that are set to at least one default delay value. A method for reducing clock skews, the method includes providing a clock tree that includes a set of variable delay components. The method is characterized by selecting a first set of variable delay components in view of timing violations occurring due clock skews, setting delay values of variable delay components that form a first set of variable delay components by programming fuses, and setting delay values of variable delay components that form a second set of variable delay components to at least one default value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.