Estimation of non-linear distortion in memory devices
US8060806B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2007 |
| Grant date | Nov 15, 2011 |
| Priority date | — |
| Expiry date | Oct 15, 2028 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C27/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory (24) includes storing data in analog memory cells (32) of the memory by writing respective analog values to the analog memory cells. A set of the analog memory cells is identified, including an interfered cell having a distortion that is statistically correlated with the respective analog values of the analog memory cells in the set. A mapping is determined between combinations of possible analog values of the analog memory cells in the set and statistical characteristics of composite distortion levels present in the interfered memory cell. The mapping is applied so as to compensate for the distortion in the interfered memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.