Minimizing impact of design changes for integrated circuit designs

US8060845B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Robert D. Herzl · South Burlington, US
• Robert S. Horton · Colchester, US
• Kenneth A. Lauricella · Colchester, US
• David W. Milton · Underhill, US
• Clarence R. Ogilvie · Waterbury, US
• Paul M. Schanely · South Burlington, US
• Nitin Sharma · Kenosha, US
• Tad J. Wilder · South Hero, US
• Charles B. Winn · Colchester, US

Key dates

• Filing date: Jul 15, 2008
• Grant date: Nov 15, 2011
• Expiry date: Nov 6, 2028

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/327
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method is provided for updating an existing netlist to reflect a design change. A register transfer level (RTL) design incorporating the design change and the existing netlist are provided to a synthesis tool. The existing netlist is set to a read-only condition to prevent a change to the existing netlist. The design and the read-only existing netlist are processed with the synthesis tool reusing logic structures from the read-only existing netlist by performing an optimization of the design and the read-only existing netlist with an objective to minimize the design space. The optimization is constrained by the read-only existing netlist. A result is generated by the synthesis tool including the existing netlist and a new portion of a netlist reflecting the design change.